Development Trend of DC/DC Converter

　　In order to obtain higher speed and better performance with lower power consumption, semiconductor devices are developing to 1V working voltage, which also puts forward higher requirements for DC/DC converters. Because portable products will be the first to adopt 1V operation Therefore, the challenge to the efficiency and power density of the power adapter is more severe. In addition to adding more functions, it is also necessary to extend the service life of the battery and reduce the system size. As the internal functions of the portable system increase, such as higher Higher memory, faster processing speed, higher Internet access bandwidth, and higher requirements for power adapters. The improvement of power adapter efficiency means that the new generation of portable systems needs to withstand exponentially increasing current, the system is small in size, and the heat dissipation capacity It is more likely to cause overheating. Therefore, system heat dissipation becomes a concern. It is very difficult to maintain high electrical efficiency at a voltage of Uo=1V. If the difference between input and output voltage increases, it is more difficult to obtain high performance ｡For this, it is necessary to find a solution suitable for high-performance, small-size, and long-running portable systems.

　　Notebook computers are one of the portable systems that require low working voltage. The core CPU of these systems requires Um=2.1V and Uo=1.3V for DC/DC application systems, and the output current is usually as high as 15A, so it tends to use 1V working voltage to reduce Power consumption. Low-power portable systems may first use a voltage of U=1V. Hand-held portable systems such as PDAs are extremely sensitive to the increase in power dissipation. These devices are usually extremely small in size. As the functions continue to increase, heat dissipation becomes The first problem to be solved.

　　Challenges faced by 1.1V power adapters

　　Many portable systems use synchronous compensation DC/DC topology. However, as the output voltage continues to decrease and the input voltage to output voltage ratio U/U increases, it becomes more difficult to design high-efficiency converters. Due to Ua/Ua and DC/DC The duty cycle of the power MOSFET in the converter is proportional. The more the output voltage is reduced, the longer the on-time of the synchronous FET (VT2) will be, and the greater the effect of switching loss on the control FET (VT1). At present, some systems The duty cycle of the synchronous FET is close to 95%, and the control FET is close to 5%. If the duty cycle of the control FET is further reduced, it will be difficult to control the DC/DC converter, and the on-time of the synchronous FET will increase. In some cases Therefore, the on-resistance of the synchronous FET is required to be very low, so that it is necessary to use two devices in parallel instead of a traditional one. However, with the increasing demand for power density, the shrinking of the system volume is contrary to the increase of devices. It can be seen that the optimization of power semiconductors not only includes improving power density, increasing efficiency, reducing the number of components, reducing motherboard space, but also reducing the complexity of motherboard design, reducing design workload, etc. These factors will promote portable systems to Uoa= With the development of 1V working voltage, it is necessary to improve system functions, increase battery life and reduce size.

　　2. Optimize the performance of power semiconductor Iv power adapter

　　For power semiconductor devices with Uout=1V, the duty cycle of U/U=control FET is extremely low, so there are special requirements for switching characteristics. The parameter that needs to be optimized is the switching charge Qw. The transfer of charge during the switching process will cause power dissipation Therefore, Qsw should be reduced as much as possible to reduce switching loss and reduce the loss of the entire device. The goal of reducing Qw and Rosone is to reduce the overall figure of merit (FOM). However, reducing these two parameters will affect other parameters, so you must choose The best silicon platform technology.

　　The synchronous FET has a very long duty cycle and very high peak current, so Ro should be reduced as much as possible. This is an important quality factor of the synchronous FET. When the control FET is turned on, the switching voltage (the source voltage of the control FET, the synchronous FET's Drain voltage) continues to rise with the increase of du/dt, and the dv/dt value may rise too fast, resulting in coupling with the parasitic capacitance C of the synchronous FET, thereby generating a voltage peak at the gate of the synchronous FET. If this peak value is greater than The threshold voltage, the synchronous FET will be turned on. Since both the control FET and the synchronous FET are turned on, the input power adapter will be short-circuited, which will greatly damage the circuit performance and cause overheating and other malfunctions. The charge ratio of the synchronous FET can be optimized ( QD/Qos<1) to avoid unexpected turn-on caused by dv/dt. Qs is the front gate critical charge.

　　The synchronous compensation topology also improves the dead time by paralleling Schottky diodes and synchronous FETs. Dead time refers to the internal delay between FET switching signals to avoid shoot-through. Because Schottky's U value is lower than the FET's own diode Therefore, during the conduction process during the dead time, the current flows through the Schottky instead of the synchronous FET's own diode. The lower U1 is, the greater the impact on the dead time. The self-contained Schottky in parallel Induction may cause the Schottky U value to increase or even offset the advantage of Schottky to the FET's own diode. Therefore, Schottky self-induction should be controlled at a low level, and the printed circuit board design should be optimized to maximize Reduce or eliminate stray inductance.

　　3. The existing 1V power adapter solution

　　IR's dual Fetkytmirf7901Dl solution integrates all power semiconductor devices in a single SO8 package, UO=1V, working efficiency exceeds 85%, and can save 60% of the motherboard area, so that the power density of the dual FETKY solution is greatly improved. This device Fully optimized MOSFET and Schottky semiconductor, suitable for synchronous compensation DC/DC converter of portable system requiring output current up to 5A.

　　The FETKY package is equipped with an interconnection structure that connects the control FET, synchronous FET and Schottky diode, thus simplifying the complexity of the circuit board design and helping to reduce the area occupied by the external printed circuit board and the stray inductance of the interconnection device ｡Compared with the discrete solution, the integrated solution reduces the space occupied by the motherboard by 60%.

　　Dual DUALFETKY has a peak circuit efficiency of about 87% in a 1V operating environment, which can solve the design problem of low-power applications.

　　As the 1V working environment extends from low-power portable systems to high-power systems, truly optimized power semiconductor devices should be selected to enhance system performance. The dual FETKY solution can improve the performance of application systems with operating voltages as low as Uour=1V.

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